\doxysubsubsection{Peripheral\+\_\+registers\+\_\+structures }
\hypertarget{group___peripheral__registers__structures}{}\label{group___peripheral__registers__structures}\index{Peripheral\_registers\_structures@{Peripheral\_registers\_structures}}
\doxysubsubsubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_a_d_c___type_def}{ADC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Analog to Digital Converter. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_a_d_c___common___type_def}{ADC\+\_\+\+Common\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_v_r_e_f_b_u_f___type_def}{VREFBUF\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em VREFBUF. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_d_c_a_n___global_type_def}{FDCAN\+\_\+\+Global\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em FD Controller Area Network. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_t_t_c_a_n___type_def}{TTCAN\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em TTFD Controller Area Network. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def}{FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em FD Controller Area Network. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_e_c___type_def}{CEC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Consumer Electronics Control. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_o_r_d_i_c___type_def}{CORDIC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em COordincate Rotation DIgital Computer. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_r_c___type_def}{CRC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em CRC calculation unit. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_r_s___type_def}{CRS\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Clock Recovery System. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_a_c___type_def}{DAC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Digital to Analog Converter. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_f_s_d_m___filter___type_def}{DFSDM\+\_\+\+Filter\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DFSDM module registers. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_f_s_d_m___channel___type_def}{DFSDM\+\_\+\+Channel\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DFSDM channel configuration registers. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_b_g_m_c_u___type_def}{DBGMCU\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Debug MCU. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_c_m_i___type_def}{DCMI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DCMI. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_p_s_s_i___type_def}{PSSI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em PSSI. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\+\_\+\+Stream\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DMA Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_b_d_m_a___channel___type_def}{BDMA\+\_\+\+Channel\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_b_d_m_a___type_def}{BDMA\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_d_m_a_m_u_x___channel___type_def}{DMAMUX\+\_\+\+Channel\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_d_m_a_m_u_x___channel_status___type_def}{DMAMUX\+\_\+\+Channel\+Status\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_d_m_a_m_u_x___request_gen___type_def}{DMAMUX\+\_\+\+Request\+Gen\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_d_m_a_m_u_x___request_gen_status___type_def}{DMAMUX\+\_\+\+Request\+Gen\+Status\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_m_d_m_a___type_def}{MDMA\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em MDMA Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_m_d_m_a___channel___type_def}{MDMA\+\_\+\+Channel\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_d_m_a2_d___type_def}{DMA2\+D\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DMA2D Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_e_t_h___type_def}{ETH\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Ethernet MAC. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_e_x_t_i___type_def}{EXTI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em External Interrupt/\+Event Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_e_x_t_i___core___type_def}{EXTI\+\_\+\+Core\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em This structure registers corresponds to EXTI\+\_\+\+Typdef CPU1/\+CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI\+\_\+\+D1/\+EXTI\+\_\+\+D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI\+\_\+\+D1 and EXTI\+\_\+\+D2 bases addresses are calculated to point to CPUx first register\+: IMR1 in case of EXTI\+\_\+\+D1 that is addressing CPU1 (Cortex-\/\+M7) C2\+IMR1 in case of EXTI\+\_\+\+D2 that is addressing CPU2 (Cortex-\/\+M4) Note\+: EXTI\+\_\+\+D2 and corresponding C2\+IMRx, C2\+EMRx and C2\+PRx registers are available for Dual Core devices only. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_l_a_s_h___type_def}{FLASH\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em FLASH Registers. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_a_c___type_def}{FMAC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Filter and Mathematical ACcelerator. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_c___bank1___type_def}{FMC\+\_\+\+Bank1\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Flexible Memory Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_c___bank1_e___type_def}{FMC\+\_\+\+Bank1\+E\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Flexible Memory Controller Bank1E. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_c___bank2___type_def}{FMC\+\_\+\+Bank2\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Flexible Memory Controller Bank2. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_c___bank3___type_def}{FMC\+\_\+\+Bank3\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Flexible Memory Controller Bank3. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def}{FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Flexible Memory Controller Bank5 and 6. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_g_p_i_o___type_def}{GPIO\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em General Purpose I/O. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_o_p_a_m_p___type_def}{OPAMP\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Operational Amplifier (OPAMP) \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_s_y_s_c_f_g___type_def}{SYSCFG\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em System configuration controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_i2_c___type_def}{I2\+C\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Inter-\/integrated Circuit Interface. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_i_w_d_g___type_def}{IWDG\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Independent WATCHDOG. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_l_t_d_c___type_def}{LTDC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em LCD-\/\+TFT Display Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_l_t_d_c___layer___type_def}{LTDC\+\_\+\+Layer\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em LCD-\/\+TFT Display layer x Controller. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_p_w_r___type_def}{PWR\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Power Control. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_c_c___type_def}{RCC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Reset and Clock Control. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_t_c___type_def}{RTC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Real-\/\+Time Clock. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_s_a_i___type_def}{SAI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Serial Audio Interface. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_s_a_i___block___type_def}{SAI\+\_\+\+Block\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def}{SPDIFRX\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em SPDIF-\/\+RX Interface. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_s_d_m_m_c___type_def}{SDMMC\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Secure digital input/output Interface. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_l_y_b___type_def}{DLYB\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Delay Block DLYB. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_h_s_e_m___type_def}{HSEM\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em HW Semaphore HSEM. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_h_s_e_m___common___type_def}{HSEM\+\_\+\+Common\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Serial Peripheral Interface. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_d_t_s___type_def}{DTS\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em DTS. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em TIM. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_l_p_t_i_m___type_def}{LPTIM\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em LPTIMIMER. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_o_m_p_o_p_t___type_def}{COMPOPT\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Comparator. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_c_o_m_p___type_def}{COMP\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_c_o_m_p___common___type_def}{COMP\+\_\+\+Common\+\_\+\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_u_s_a_r_t___type_def}{USART\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Universal Synchronous Asynchronous Receiver Transmitter. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_s_w_p_m_i___type_def}{SWPMI\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Single Wire Protocol Master Interface SPWMI. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_w_w_d_g___type_def}{WWDG\+\_\+\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em Window WATCHDOG. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_a_m_e_c_c___monitor_type_def}{RAMECC\+\_\+\+Monitor\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em RAM\+\_\+\+ECC\+\_\+\+Specific\+\_\+\+Registers. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_r_a_m_e_c_c___type_def}{RAMECC\+\_\+\+Type\+Def}}
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}
